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IDT T M InterpriseT M Integrated Communications Processor
RC32434
Device Overview
The RC32434 is a member of the IDTTM InterpriseTM family of PCI integrated communicatio ns processors. It incorporates a hig h performance CPU core and a number of on-chip peripherals. The integrated processor is designed to transfer information from I/O modules to main memory with minimal CPU interventio n, usin g a highly sophisticated direct memory access (DMA) engin e. All data transfers through the RC32434 are achieved by writing data from an on-chip I/O peripheral to main memory and then out to another I/O module.
Features
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32-bit CPU Core - MIPS32 instruction set - Cache Sizes: 8KB instruction and data caches, 4-Way set associative, cache line locking, non-blocking prefetches - 16 dual-entry JTLB with varia ble page sizes - 3-entry instruction TLB - 3-entry data TLB - Max is sue rate of one 32x16 mult ip ly per clock - Max is sue rate of one 32x32 mult ip ly every other clo ck - CPU control with start, stop, and single stepping - Software breakpoints support - Hardware breakpoints on virtual addresses - ICE Interface that is compatible with v2.5 of the EJTAG Specification
PCI Interface - 32-bit PCI revision 2.2 complia nt - Supports host or satellite operation in both master and target modes - Support for synchronous and asynchronous operation - PCI clock supports frequencies from 16 MHz to 66 MHz - PCI arbiter in Host mode: supports 6 external masters, fixed priority or round robin arbitratio n - I2 O "like" PCI Messaging Unit x Ethernet Interface - 10 and 100 Mb/s ISO/IEC 8802-3:1996 compliant - Supports MII or RMII PHY interface - Supports 64 entry hash table based multicast address filtering - 512 byte transmit and receive FIFOs - Supports flow control functions outlined in IEEE Std. 802.3x1997 x DDR Memory Controller - Supports up to 256MB of DDR SDRAM - 1 chip select supporting 4 internal DDR banks - Supports a 16-bit wide data port using x8 or x16 bit wide DDR SDRAM devices - Supports 64 Mb, 128 Mb, 256 Mb, 512 Mb, and 1Gb DDR SDRAM devices - Data bus multiplexing support allows interfacing to standard DDR DIMMs and SODIMMs - Automatic refresh generation
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Block Diagram
MM II/R II
MIP S-32 CPU Core ICE
ET J AG DCc . a he MU M I C he . ac
In rru te pt C nt r o rolle
: : 1E e e th rn t 10 00 /1 In rfac te e
3C nt ou er T ers im IP s Bu TM
NVR AM C ontro lle r
PMB us DR D (1 it) 6-b DR D Cn o trolle rs
DA M Cn o trolle r
Arb iter
M m ry &I/ eo O C tro on ller
B /S s m us y te In grity te M itor on
1U R AT (16 0) 55
G IO P I rfa nte ce
SI P C tro on ller
PI C M s T rge a ter/ a t In ac terf e
P IA r C rbite (H t M e) os od
Mm & e ory P eriph l Bu (8 era s -bit)
Se l C an l ria h ne
G IOP P ins
S IB P us
P IB C us
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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20 04 Integrated Device Techno logy, In c.
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DSC 6214
IDT RC32434
Non-Volatile RAM - Provides 512-bits of non-vola tile storage - Eliminates need for external boot configuration vector - Stores in itial PCI config uration register values when PCI configured to operate in satellite mode with suspended CPU execution - Authorization unit ensures only authorized software will operate on the system x Memory and Peripheral Device Controller - Provides "glueless" interface to standard SRAM, Fla sh, ROM, dual-port memory, and peripheral devices - Demultiplexed address and data buses: 8-bit data bus, 26-bit address bus, 4 chip selects, control for external data bus buffers Automatic byte gathering and scattering - Flexible protocol config uration parameters: programmable number of wait states (0 to 63), programmable postread/postwrit e delay (0 to 31), supports external wait state generation, supports Intel and Motorola style peripherals - Write protect capability per chip select - Programmable bus transactio n timer generates warm reset when counter expires - Supports up to 64 MB of memory per chip sele ct x DMA Controller - 6 D MA channels: two channels for PCI (PCI to Memory and Memory to PCI), two channels for the Ethernet in terface, and two channels for memory to memory DMA operations - Provides flexible descriptor based operation - Supports unaligned transfers (i.e., source or destinatio n address may be on any byte boundary) with arbitrary byte length x Universal Asynchronous Receiver Transmitter (UART) - Compatib le wit h the 16550 and 16450 UARTs - 16-byte transmit and receive buffers - Programmable baud rate generator derived from the system clock - Fully programmable serial characteris tics: - 5, 6, 7, or 8 bit characters - Even, odd or no parity bit generation and detection - 1, 1-1/2 or 2 stop bit generation - Line break generation and detection - False start bit detection - Internal lo opback mode x Additional General Purpose Peripherals - Interrupt controller - System in tegrity functions - General purpose I/O controller - Seria l peripheral interface (SPI) x Counter/Timers - Three general purpose 32-bit counter timers - Timers may be cascaded - Selectable counter/timer clo ck source x JTAG Interface - Compatib le wit h IEEE Std. 1149.1 - 1990
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Core CPU Execution Cor e The 32-bit CPU core is 100% compatible with the MIPS32 instruction set architecture (ISA). Specifically, this device features the 4Kc CPU core developed by MIPS Technologies Inc. (www.mips.com). This core issues a single instruction per cycle, includes a five stage pipeline and is optimized for applications that require integer arithmetic. The CPU core inclu des 8 KB instruction and 8 KB data caches. Both caches are 4-way set associative and can be locked on a per line basis, which allows the programmer control over this precious on-chip memory resource. The core also features a memory management unit (MMU). The CPU core also incorporates an enhanced join t test access group (EJTAG) interface that is used to interface to in-circuit emulator tools, providing access to internal registers and enabling the part to be controlled externally, simplifying the system debug process. The use of this core allows IDT's customers to le verage the broad range of software and development tools available for the MIPS architecture, inclu ding operatin g systems, compilers, and in-circuit emula tors. PCI Interface The PCI interface on the RC32434 is compatible wit h version 2.2 of the PCI specification. An on-chip arbit er supports up to six external bus masters, supporting both fixed priority and rotating priority arbitration schemes. The part can support both satellit e and host PCI configurations, enabling the RC32434 to act as a slave controller for a PCI add-in card application or as the primary PCI controller in the system. The PCI interface can be operated synchronously or asynchronously to the other I/O interfaces on the RC32434 device. Ethernet Interface The RC32434 has one Ethernet Channel supportin g 10Mbps and 100Mbps speeds to provide a standard media independent interface (MII or RMII), allo wing a wide range of external devices to be connected efficiently. Double Data Rate Memory Controller The RC32434 incorporates a high performance double data rate (DDR) memory controller whic h supports x16 memory configurations up to 256MB. This module provid es all of the signals required to interface to discrete memory devices, including a chip sele ct, dif ferentia l clocking outputs and data strobes. I/ Controller M emory and I/O Controlle r The RC32434 uses a dedicated local memory/IO controller including a de-multiple xed 8-bit data and 26-bit address bus. It includes all of the signals required to interface directly to a maximum of four Intel or Motorola-style external peripherals .
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IDT RC32434
DMA Controller The DMA controller consis ts of 6 independent DMA channels, all of which operate in exactly the same manner. The DMA controller off-loads the CPU core from moving data among the on-chip interfaces, external perip herals, and memory. The controller supports scatter/gather DMA wit h no alig nment restrictions, making it appropriate for communications and graphic s systems. UART Interface The RC32434 contains a serial channel (UART) that is compatible wit h the industry standard 16550 UART. General Purpose I/O Controller The RC32434 has 14 general purpose in put/output pins. Each pin may be used as an active high or active low level interrupt or nonmaskable interrupt input, and each signal may be used as a bit input or output port. System Integrity Functions The RC32434 contains a programmable watchdog timer that generates a non-maskable interrupt (NMI) when the counter expires and also contains an address space monit or that reports errors in response to accesses to undecoded address regions.
Thermal T hermal Considerations
The RC32434 is guaranteed in an ambient temperature range of 0 to +70 C for commercial temperature devices and - 40 to +85 for industrial temperature devices.
History Revision History
November 3, 2003: Initial publication. Preliminary Information. December 15, 2003: Fin al version. In Table 7, changed maximum value for Tskew in 266MHz category and changed values for Tdo in all speed grades for signals DDRADDR, etc. In Table 8, changed minimum values in all speed grades for all Tdo signals and for Tsu and Tzd in MDATA[7:0]. In Table 16, added reference to Power Considerations document. In Table 17, added 2 rows under PCI and Notes 1 and 2. January 5, 2004: In Table 19, Pin F6 was changed from Vcc I/O to Vss. In Table 23, pin F6 was deleted from the Vcc I/O row and added to the Vss row. January 27, 2004: In Table 3, revised description for MADDR[3:0] and changed 4096 cycles to 4000 for MADDR[7]. (Note: MADDR was incorrectly labeled as MDATA in previous data sheet.) March 29, 2004: Added Standby mode to Table 16, Power Consumption.
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IDT RC32434
Pin Description Table
The following table lists the functions of the pins provid ed on the RC32434. Some of the functions listed may be multiple xed onto the same pin. The active polarity of a sig nal is defin ed using a suffix. Signals endin g with an "N" are defined as being active, or asserted, when at a logic zero (low) level. All other sig nals (including clo cks, buses, and select lin es) will be in terpreted as being active, or asserted, when at a logic one (high) le vel.
Signal
Type
Name/Description
Memory and Peripheral Bus BDIRN O External Buffer Direction. Controls the direction of the external data bus buffer for the memory and peripheral bus. I f t he RC32434 memory and peripheral bus is connected to the A side of a transceiver, such as an IDT74FCT245, then this pin may be directly connected to the direction control (e. g., BDIR) pin of the transceiver. External Buffer Enable. This signal provides an output enable control for an external buffer on the memory and peripheral data bus. Write Enables. This signal is the memory and peripheral bus write enable signal. Chip Selects. These signals are used to select an external device on the memory and peripheral bus. Address Bus. 22-bit memory and peripheral bus address bus. MADDR[25:22] are available as GPIO alternate functions. Data Bus. 8-bit memory and peripheral data bus. During a cold reset, these pins function as inputs that are used to load t he boot configurat ion vector. Output Enable. This signal is asserted when data should be driven by an external device on the memory and peripheral bus. Read Write. This signal indicates whether the transaction on the memory and peripheral bus is a read transaction or a write transaction. A high level indicates a read from an external device. A low level indicates a write to an external device. Wait or Transfer Acknowledge. When configured as wait, this signal is asserted during a memory and peripheral bus transaction to extend the bus cycle. When configured as a transfer acknowledge, this signal is asserted during a transaction to signal the completion of the transaction.
BOEN WEN CSN[3:0] MADDR[21:0] MDATA[7:0] OEN RWN
O O O O I/O O O
WAITACKN
I
DDR Bus DDRADDR[13:0] DDRBA[1:0] DDRCASN DDRCKE O O O O DDR Address Bus. 14-bit multiplexed DDR address bus. This bus is used to transfer the addresses to the DDR devices. DDR Bank Address. These signals are used t o transfer the bank address to the DDRs. DDR Column Address Strobe. This signal s asserted during DDR transaci tions. DDR Clock Enable. The DDR clock enable signal is asserted during normal DDR operation. This signal is negated following a cold reset or during a power down operation. DDR Negative DDR clock. This signal is the negative clock of the dif ferential DDR clock pair. Tabl e 1 Pin Description (Part 1 of 6)
DDRCKN
O
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IDT RC32434 Signal DDRCKP DDRCSN DDRDATA[15:0] DDRDM[ 1:0] Type O O I/O O Name/Description DDR Positive DDR clock. This signal is the positive clock of the differential DDR clock pair. DDR Chip Selects. This active low signal is used to select DDR device(s) on the DDR bus. DDR Data Bus. 16-bit DDR data bus is used to transfer data between the RC32434 and the DDR devices. Data is transferred on both edges of the clock. DDR Data Write Enables. Byte data write enables are used to enable specific byte lanes during DDR writes. DDRDM[0] corresponds to DDRDATA[7:0] DDRDM[1] corresponds to DDRDATA[15:8] DDR Data Strobes. DDR byte data st robes are used to clock data between DDR devices and the RC32434. These strobes are inputs during DDR reads and outputs during DDR writes. DDRDQS[0] corresponds to DDRDATA[7:0] DDRDQS[1] corresponds to DDRDATA[15:8] DDR Row Address Strobe. The DDR row address strobe is asserted during DDR transactions. DDR Voltage Reference. SSTL_2 DDR voltage reference is generated by an external source. DDR Write Enable. DDR write enable is asserted during DDR write transactions.
DDRDQS[1:0]
I/O
DDRRASN DDRVREF DDRWEN PCI Bus PCIAD[31:0]
O I O
I/O
PCI Multiplexed Address/Data Bus. Address is driven by a bus master during initial PCIFRAMEN assertion. Data is then driven by the bus master during writes or by the bus target during reads. PCI Multiplexed Command/Byte Enable Bus. PCI commands are driven by the bus mast er during the initial PCIFRAMEN assertion. Byte enable signals are driven by the bus master during subsequent dat a phase(s). PCI Cl ock. Clock used for all PCI bus transactions. PCI Device Select. This signal is driven by a bus target to indicate that the target has decoded the address as one of its own address spaces. PCI Frame. Driven by a bus master. Assertion indicates the beginning of a bus transaction. Negation indicates the last data. PCI Bus Grant. In PCI host mode with internal arbiter: The assertion of these signals indicates to the agent that the internal RC32434 arbiter has granted the agent access to the PCI bus. In PCI host mode with external arbiter: PCIGNTN[0]: asserted by an ext ernal arbiter to indicate to the RC32434 that access to the PCI bus has been granted. PCIGNTN[3:1]: unused and driven high. In PCI satellite mode: PCIGNTN[0]: This signal is asserted by an external arbiter to indicate to the RC32434 that access to the PCI bus has been granted. PCIGNTN[3:1] : unused and driven high. PCI Initiator Ready. Driven by the bus master to indicat e that t he current datum can complete. Tabl e 1 Pin Description (Part 2 of 6)
PCICBEN[3:0]
I/O
PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[3:0]
I I/O I/O I/O
PCIIRDYN
I/O
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IDT RC32434 Signal PCILOCKN PCIPAR Type I/O I/O Name/Description PCI Lock. This signal is asserted by an external bus master to indicate that an exclusive operation is occurring. PCI Parity. Even parity of the PCIAD[31:0] bus. Driven by the bus master during address and write Dat a phases. Driven by the bus target during the read data phase. PCI Parity Error. If a parity error is detected, this signal is asserted by the receiving bus agent 2 clocks after the data is received. PCI Bus Request. In PCI host mode with internal arbiter: These signals are inputs whose assertion indicates to the internal RC32434 arbiter that an agent desires ownership of t he PCI bus. In PCI host mode with external arbiter: PCIREQN[0]: asserted by the RC32434 t o request ownership of the PCI bus. PCIREQN[3:1]: unused and driven high. In PCI satellite mode: PCIREQN[0]: this signal is asserted by the RC32434 to request use of t he PCI bus. PCIREQN[1]: f unction changes to PCIIDSEL and is used as a chip select during configuration read and write transactions. PCIREQN[3:2]: unused and driven high. PCI Reset. In host mode, this signal is asserted by the RC32434 to generate a PCI reset . In satellite mode, assertion of this signal initiates a warm reset. PCI System Error. This signal is driven by an agent to indicate an address parit y error, data parity error during a special cycle command, or any other system error. Requires an external pull-up. PCI Stop. Driven by the bus target to terminate the current bus transaction. For example, to indicate a retry. PCI Target Ready. Driven by the bus target t o indicate that the current data can complete.
PCIPERRN PCIREQN[3:0]
I/O I/O
PCIRSTN PCISERRN
I/O I/O
PCISTOPN PCITRDYN
I/O I/O
General Purpose Input/Output GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0SOUT Alternate function: UART channel 0 serial output . General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0SINP Alternate function: UART channel 0 serial input. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0RTSN Alternate function: UART channel 0 request to send. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0CTSN Alternate function: UART channel 0 clear to send. Tabl e 1 Pin Description (Part 3 of 6)
GPIO[1]
I/O
GPIO[2]
I/O
GPIO[3]
I/O
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IDT RC32434 Signal GPIO[4] Type I/O Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: MADDR[22] Alternate function: Memory and peripheral bus address. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: MADDR[23] Alternate function: Memory and peripheral bus address. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: MADDR[24] Alternate function: Memory and peripheral bus address. The value of this pin may be used as a counter timer clock input (see Counter Timer Clock Select Register in Chapter 14, Counter/Timers, of the RC32434 User Manual). General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: MADDR[25] Alternate function: Memory and peripheral bus address. The value of this pin may be used as a counter timer clock input (see Counter Timer Clock Select Register in Chapter 14, Counter/Timers, of the RC32434 User Manual). General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: CPU Alternate function: CPU or DMA debug output pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIREQN[4] Alternate function: PCI Request 4. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIGNTN[4] Alternate function: PCI Grant 4. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIREQN[5] Alternate function: PCI Request 5. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIGNTN[5] Alternate function: PCI Grant 5. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIMUINTN Alternate function: PCI Messaging unit interrupt output.
GPIO[5]
I/O
GPIO[6]
I/O
GPIO[7]
I/O
GPIO[8]
I/O
GPIO[9]
I/O
GPIO[10]
I/O
GPIO[11]
I/O
GPIO[12]
I/O
GPIO[13]
I/O
SPI Interface SCK I/O Serial Clock. This signal is used as the serial clock output. This pin may be used as a bit input/output port. Tabl e 1 Pin Description (Part 4 of 6)
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IDT RC32434 Signal SDI SDO Ethernet Interfaces MIICL MIICRS MIIRXCLK I I I Ethernet MII Collision Detected. This signal is asserted by the ethernet PHY when a collision is det ected. Ethernet MII Carrier Sense. This signal is asserted by the ethernet PHY when either the transmit or receive medium is not idle. Ethernet MII Receive Clock. This clock is a continuous clock that provides a timing reference for the reception of data. This pin also functions as the RMII REF_CLK input. Ethernet MII Receive Data. This nibble wide data bus contains the data received by the ethernet PHY. This pin also functions as the RMII RXD[1:0] input. Ethernet MII Receive Data Valid. The assert ion of this signal indicates that valid receive data is in the MII receive data bus. This pin also functions as the RMII CRS_DV input. Ethernet MII Receive Error. The assertion of this signal indicates that an error was detected somewhere in the ethernet frame currently being sent in the MII receive data bus. This pin also functions as the RMII RX_ER input. Ethernet MII Transmit Clock. This clock is a continuous clock that provides a timing reference for the transfer of transmit data. Ethernet MII Transmit Data. This nibble wide data bus contains the dat a to be transmitted. This pin also functions as the RMII TXD[1:0] output. Ethernet MII Transmit Enable. The assertion of this signal indicat es that data is present on the MII for transmission. This pin also functions as the RMII TX_EN output. Ethernet MII Transmit Coding Error. When this signal is asserted together with MIITXENP, the ethernet PHY will transmit symbols which are not valid dat a or delimiters. MII Management Data Clock. This signal is used as a timing reference for transmission of data on the management interface. MII Management Data. This bidirectional signal is used to transfer data between the station management entity and the ethernet PHY. Type I/O I/O Name/Description Serial Data Input. This signal is used to shift in serial data. This pin may be used as a bit input/output port. Serial Data Output. This signal is used shift out serial data.
MIIRXD[3:0]
I
MIIRXDV
I
MIIRXER
I
MIITXCLK MIITXD[3:0]
I O
MIITXENP
O
MIITXER
O
MIIMDC MIIMDIO EJTAG / JTAG JTAG_TMS
O I/O
I
JTAG Mode. The value on this signal controls the t est mode select of the boundary scan logic or JTAG Controller. When using the EJTAG debug interface, this pin should be left disconnected (since there is an internal pull-up) or driven high. EJTAG Mode. The value on this signal controls the test mode select of the EJTAG Controller. When using the JTAG boundary scan, this pin should be left disconnected (since there is an internal pull-up) or driven high. Tabl e 1 Pin Description (Part 5 of 6)
EJTAG_TMS
I
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IDT RC32434 Signal JTAG_TRST_N Type I Name/Description JTAG Reset. This active low signal asynchronously resets the boundary scan logic, JTAG TAP Controller, and the EJTAG Debug TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board 3) clock JTAG_TCK while holding EJTAG_TMS and/or JTAG_TMS high. JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic, JTAG Controller, or the EJTAG Controller. JTAG_TCK is independent of the system and the processor clock with a nominal 50% duty cycle. JTAG Data Output. This is the serial data shifted out from the boundary scan logic, JTAG Cont roller, or the EJTAG Controller. When no dat a is being shifted out, this signal is tri-stated. JTAG Data Input. This is the serial data input to the boundary scan logic, JTAG Controller, or t he EJTAG Controller.
JTAG_TCK
I
JTAG_TDO
O
JTAG_TDI System CLK
I
I
Master Clock. This is the master clock input. The processor frequency is a multiple of this clock frequency. This clock is used as the system clock for all memory and peripheral bus operations. Load External Boot Configuration Vector. When this pin is asserted (i.e., high) the boot configuration vector is loaded from an externally supplied value during a cold reset. When this pin is negated, the boot configuration vector is taken from the NVRAM located on-chip. External Clock. This clock is used for all memory and peripheral bus operations. Cold Reset. The assertion of this signal init iates a cold reset. This causes the processor state to be initialized, boot configuration to be loaded, and the internal PLL to lock onto the master clock (CLK). Reset. The assertion of this bidirectional signal initiates a warm reset. This signal is asserted by the RC32434 during a warm reset. Tabl e 1 Pin Description (Part 6 of 6)
EXTBCV
I
EXTCLK COLDRSTN
O I
RSTN
I/O
Pin Characteristics
Note: Some in put pads of the RC32434 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal in puts (such as WAITACKN) which, if left flo ating, could adversely affect the RC32434's operatio n. Als o, any input pin left floating can cause a slight increase in power consumption.
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IDT RC32434
Function Memory and Peripheral Bus
Pin Name BDIRN BOEN WEN CSN[3:0] MADDR[21:0] MDATA[7:0] OEN RWN WAITACKN DDRADDR[13:0] DDRBA[1:0] DDRCASN DDRCKE DDRCKN DDRCKP DDRCSN DDRDATA[15:0] DDRDM[ 1:0] DDRDQS[1:0] DDRRASN DDRVREF DDRWEN PCIAD[31:0] PCICBEN[3:0] PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[3:0] PCIIRDYN PCILOCKN PCIPAR PCIPERRN PCIREQN[3:0] PCIRSTN PCISERRN PCISTOPN PCITRDYN GPIO[ 8:0] GPIO[ 13:9] SCK SDI SDO
Type O O O O I/O I/O O O I O O O O O O O I/O O I/O O I O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL SSTL_2 SSTL_2 SSTL_2 SSTL_2 / LVCMOS SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 SSTL_2 Analog SSTL_2 PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI LVTTL PCI LVTTL LVTTL LVTTL
I/O Type High Drive High Drive High Drive High Drive High Drive High Drive High Drive High Drive STI
Internal Resistor
Notes1
pull-up
DDR Bus
PCI Bus Interface
pull-up pull-up pull-up pull-up
on board on board on board on board
Open Collector
pull-up on board pull-down on board pull-up on board pull-up on board pull-up on board pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up on board on board on board on board
General Purpose I/O Serial Peripheral Interface
High Drive High Drive High Drive High Drive
Table 2 Pin Characteristics (Part 1 of 2)
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IDT RC32434 Function Ethernet Interfaces Pin Name MIICL MIICRS MIIRXCLK MIIRXD[3:0] MIIRXDV MIIRXER MIITXCLK MIITXD[3:0] MIITXENP MIITXER MIIMDC MIIMDIO JTAG_TMS EJTAG_TMS JTAG_TRST_N JTAG_TCK JTAG_TDO JTAG_TDI CLK EXTBCV EXTCLK COLDRSTN RSTN Type I I I I I I I O O O O I/O I I I I O I I I O I I/O Buffer LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL I/O Type STI STI STI STI STI STI STI Low Drive Low Drive Low Drive Low Drive Low Drive STI STI STI STI Low Drive STI STI STI High Drive STI Low Drive / STI Internal Resistor pull-down pull-down pull-up pull-up pull-down pull-down pull-up Notes1
EJTAG / JTAG
pull-up pull-up pull-up pull-up pull-up pull-up pull-down
System
pull-up
pull-up on board
Table 2 Pin Characteristics (Part 2 of 2)
1. External pull-up r equired in most system applications. Some applications
may requir e additional pull-ups not identified in this table.
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IDT RC32434
Boot Configuration Vector
The encoding of the boot config uration vector is described in Table 3, and the vector in put is illustrated in Figure 4. The value of the boot configuration vector read in by the RC32434 durin g a cold reset may be determined by reading the Boot Configuration Vector (BCV) Register.
Signal MADDR[3:0]
Name/Description CPU Pipeline Clock Multiplier. This field specifies the value by which the PLL multiplies the master clock input (CLK) to obtain the processor clock frequency (PCLK). For master clock input f requency constraints, refer t o Table 3.2 in the RC32434 User Manual. 0x0 - PLL Bypass 0x1 - Multiply by 3 0x2 - Multiply by 4 0x3 - Multiply by 5 - Reserved 0x4 - Multiply by 5 0x5 - Multiply by 6 - Reserved 0x6 - Multiply by 6 0x7 - Multiply by 8 0x8 - Multiply by 10 0x9 through 0xF - Reserved External Clock Divider. This field specifies the value by which the IPBus clock (ICLK), which is always 1/2 PCLK, is divided in order to generate the external clock output on the EXTCLK pin. 0x0 - Divide by 1 0x1 - Divide by 2 0x2 - Divide by 4 0x3 - reserved Endian. This bit specifies the endianness. 0x0 - little endian 0x1 - big endian Reset Mode. This bit specifies the length of time the RSTN signal is driven. 0x0 - Normal reset: RSTN driven for minimum of 4000 clock cycles. If the internal boot configuration vector is selected, the expiration of an 18-bit counter operating at t he master clock input (CLK) frequency is used as the PLL stabilization delay. 0x1 - Reserved PCI Mode. This bit controls the operating mode of the PCI bus interface. The init ial value of the EN bit in the PCIC register is determined by the PCI mode. 0x0 - Disabled (EN initial value is zero) 0x1 - PCI satellite mode with PCI target not ready (EN initial value is one) 0x2 - PCI satellite mode with suspended CPU execution (EN initial value is one) 0x3 - PCI host mode with external arbiter (EN initial value is zero) 0x4 - PCI host mode with int ernal arbiter using fixed priority arbitration algorithm (EN init ial value is zero) 0x5 - PCI host mode with int ernal arbiter using round robin arbitration algorithm (EN init ial value is zero) 0x6 - reserved 0x7 - reserved Table 3 Boot Configuration Encoding (Part 1 of 2)
MADDR[5:4]
MADDR[6]
MADDR[7]
MADDR[10:8]
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IDT RC32434 Signal MADDR[11] Name/Description Disable Watchdog Timer. When this bit is set, the watchdog timer is disabled following a cold reset. 0x0 - Watchdog timer enabled 0x1 - Watchdog timer disabled Reserved. These pins must be driven low during boot configurat ion. Reserved. Must be set to zero. Table 3 Boot Configuration Encoding (Part 2 of 2)
MADDR[13:12] MADDR[15:14]
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IDT RC32434
Logic Diagram -- RC32434
CLK COL DRSTN RSTN EXTCLK EXTBCV BDIRN BOEN WEN CSN[3:0] MADDR[21:0] MDATA[7:0] OEN RWN WAITACKN
System Signals
4 22 8
Memory and Peripheral Bus
Ethernet
MIIMDC MIIMDIO MIICL MIICRS MIIRXCLK MIIRXD[3:0 ] MIIRXDV MIIRXER MIITXCLK MIITXD[3:0 ] MIITXENP MIITXER
14 2 4
4 16 2 2
EJTAG / JTAG Signals
JTAG_TR ST_N JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS EJTAG_TMS
DD RAD DR[1 3:0 ] DD RBA[1:0] DD RCASN DD RCKE DD RCKN DD RCKP DD RCSN DD RDATA[15:0] DD RDM[1:0] DD RDQS[1:0 ] DD RRASN DD RVR EF DD RWEN
DDR Bus
RC32434
32 4
General Purpose I/O
GPIO[13:0 ]
14
4
SPI
SDO SCK SDI
4
PCIAD[3 1:0 ] PCICBEN[3 :0] PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[3:0 ] PCIIR DYN PCILOC KN PCIPAR PCIPER RN PCIREQN[3:0] PCIRSTN PCISER RN PCISTOPN PCITRD YN
PCI Bus
VccCore VccI/O Vss VccPLL VssPLL
Power/Ground
Figure 1 Logic Diagram
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AC Timing Definitions
Below are examples of the AC timing characteris tics used throughout this document.
Tlow Tper clock Tdo Out put signal 1 Tzd Out put signal 2 Tsu Input Signal 1 Tpw Signal 1 Signal 2 Signal 3 Tskew Thld Tdz Tdo Tjitter Trise Tfall Thigh
Figure 2 AC Timing Definitions Waveform
Symbol Tper Tlow Thigh Trise Tf all Tjitter Tdo Tzd Tdz Tsu Thld Tpw Tslew X(clock) Tskew Clock period. Clock low. Amount of time the clock is low in one clock period.
Definition
Clock high. Amount of time the clock is high in one clock period. Rise time. Low to high transition time. Fall time. High to low transition time. Jitter. Amount of time the reference clock (or signal) edge can vary on either the rising or falling edges. Data out. Amount of t ime after the reference clock edge that the output will become valid. The minimum time represents t he data output hold. The maximum time represents the earliest time the designer can use the dat a. Z state to data valid. Amount of time after the reference clock edge t hat the tri-stated output takes to become valid. Data valid to Z state. Amount of time after the reference clock edge that the valid output takes to become tri-st ated. Input set-up. Amount of time before the reference clock edge that the input must be valid. Input hold. Amount of time after the reference clock edge that the input must remain valid. Pulse width. Amount of time the input or output is active for asynchronous signals. Slew rate. The rise or fall rate for a signal to go from a high to low, or low to high. Timing value. This notation represents a value of `X' multiplied by the clock time period of the specified clock. Using 5(CLK) as an example: X = 5 and the oscillator clock (CLK) = 25MHz, then the timing value is 200. Skew. The amount of time two signal edges deviate from one another. Table 4 AC Timi ng Definitions
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System Clock Parameters
(Values based on systems running at recommended supply volt ages and operating temperatures, as shown in Tables 14 and 15.)
266MHz Min 200 3.8 none 100 7.5 none 25 8.0 40 -- -- Max 266 5.0 133 10.0 125 40.0 60 3.0 0.1 300MHz Min 200 3.3 100 6.7 25 8.0 40 -- -- Max 300 5.0 150 10.0 125 40.0 60 3.0 0.1 350MHz Min 200 2.85 100 5.7 25 8.0 40 -- -- Max 350 5.0 175 10.0 125 40.0 60 3.0 0.1 400MHz Min 200 2.5 100 5.0 25 8.0 40 -- -- Max 400 5.0 200 10.0 125 40.0 60 3.0 0.1 Timing Diagr am Reference See Figure 3.
Par ameter PCLK 1
2,3,4
Symbol Frequency Tper
Reference Edge none
Units MHz ns MHz ns MHz ns % of Tper_5a ns ns
ICLK
Frequency Tper
CLK5
Frequency Tper_5a Thigh_5a, Tlow_5a Trise_5a, Tfall_5a Tjitter_5a
Table 5 Clock Parameter s
1. The CPU 2.
pipeline clock (PCLK) speed is selected during cold reset by the boot configuration vector (see Table 3). Refer to Chapter 3, Clocking and Initialization, in the RC32434 User Reference Manual for the allowable frequency r anges of CLK and PCLK. ICLK is the internal IPBus clock. It is always equal to PCLK divided by 2. This clock cannot be sampled externally. MIIxTXCLK) frequency must be equal to or less than 1/2 ICLK ( MIIxRXCLK and MIIxTXCLK <= 1/2( ICLK)) . must be equal to or less than two times ICLK (PCICLK <= 2( ICLK)) with a maximum PCICLK of 66 MHz. is input fr om the external oscillator to the internal PLL.
3. The ethernet clock (MIIxRXCLK and 4. PCICLK
5. The input clock (CLK)
Tper _5a
Thigh_5a
Tlow_5a
CLK
Tjitter_5a Tjitter_5a Trise_5a Tfall_5a
Figure 3 Clock Parameters Waveform
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AC Timing Characteristics
(Values given below are based on systems runnin g at recommended operating temperatures and supply voltages, shown in Tables 14 and 15.)
Signal Reset COLDRSTN 1
3 3
Symbol
Reference Edge
266MHz Min Max
300MHz Min Max
350MHz Min Max
400MHz Min Max
Unit
Conditions
Timing Diagram Reference
Tpw_6a2 Trise_6a
2
none none none COLDRSTN falling COLDRSTN falling RSTN falling RSTN rising
OS C --
2(CLK)
-- 5.0 -- 15.0 30.0
5(CLK)
OS C --
2(CLK)
-- 5.0 -- 15.0 30.0
5(CLK)
OSC --
2(CLK)
-- 5.0 -- 15.0 30.0
5(CLK)
OSC --
2(CLK)
-- 5.0 -- 15.0 30.0
5(CLK)
ms ns ns ns ns ns ns
Cold reset Cold reset Warm reset Cold reset Cold reset Warm reset Warm reset
See Figures 4 and 5.
RSTN (input) RSTN (output) MADDR[15:0] (boot vector)
Tpw_6b
Tdo_6c Tdz_6d2 Tdz_6d 2 Tzd_6d
2
-- -- --
2(CLK)
-- -- --
2(CLK)
-- -- --
2(CLK)
-- -- --
2(CLK)
--
--
--
--
Table 6 Reset and System AC Timing Characteristics
1. The 2. The
COLDRSTN minimum pulse width is the oscillator stabilization time (O SC) with Vcc stable. values for this symbol were determined by calculation, not by testing. It is treated as an asynchronous input.
3. RSTN is a bidirectional signal.
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IDT RC32434
1
2
3
4
5
6
CLK COLDRSTN RSTN MADDR[15:0] M ADDR[21:16] EXTCLK EX TBCV
*
Boo t Configu ra ti on Vector Dri ve n Driven
* COLDRSTNsampled negated (high) by theRC32434
1.
4000CLK
c lock c ycles
4000CLK
c lock c ycles
EXTBCV is asserted (i.e., pulle d-up). COLDRSTN i s asserted by external l ogic. The RC3243 4 re sp onds by i mmedi ately tri-stati ng the bo ttom 16-bi ts of the me mo ry and pe ri pheral ad dress bu s (MADDR[15:0]), d ri ving th e re mai ning ad dress bu s signa ls( i .e., MADDR[21:16]), and asserting RSTN. EXTCLK is un defined at this poi nt. Extern al logi c drives th e b oot configu rati on ve ctor on MADD R[1 5:0]. Extern al logi c neg ate s COLD RSTN and tri-sta tes th e b oot configu ra ti on ve ctor on MADD R[15 :0]. In re sponse, the RC32 434 stop s sampli ng the boot configu rati on ve ctor and retains the boo t configuration vector val ue se en two clock cycle s earl ier (i .e., the value on th e MADDR[15:0] li nes two rising ed ges o f CLK e arlier). Within 16 CLK clock cycles after COLDRSTN is sampled neg ate d, the R C3243 4 be gins driving MADDR[15:0]. Th e R C32434 wa its for the NVRAM to i nitiali ze (i f th e Di sable NVRAM Initial ization mode is n ot sele cted in the boot con fig uration vector) and for the PLL to sta bili ze. Th e R C32434 then beg ins g enerating EXTCL K. After at le ast 4 000 CLK clock cycle s, the RC3 2434 tri -states RSTN. At lea st 4 000 CLK clock cycles after neg ati ng RSTN, the RC32 434 samples RSTN. If RSTN i s ne gate d , cold reset h as compl ete d a nd the RC32 434 CPU b egin s executing by ta ki ng MIPS reset exce pti on.
2. 3.
4. 5. 6. 7.
Figure 4 COLD Reset Operation with External Boot Configuration Vector AC Timing Waveform
Note: For a diagram showing the COLD Reset Operation with Internal Boot Configuratio n Vector, see Figure 3.6 in the RC32434 User Reference Manual.
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IDT RC32434
1
2
3
4
5
6
CLK COLDRSTN RSTN FFFF_FFFF Activ e Deas serted Active
MDATA[7:0] Mem Control Signals
4000 CLK
cloc Cycles k
4000 CLK
clock Cyc les
1. 2. 3. 4. 5. 6.
Warm rese t condition cause d b y assertion of RSTN b y an external age nt. The RC32 434 tri -states the data bus, MDATA[7:0], n egates a ll memory control signa ls, and itself a sse rts R STN. The RC324 34 co nti nues to drive the add ress bus th rougho ut th e e nti re w arm reset. The RC32 434 n ega tes RSTN afte r 400 0 master cl ock (CLK) clock cycles. External lo gic negates R STN. The RC32 434 s amples RSTN nega ted at least 40 00 ma ster clock (CL K) clock cycle s afte r step 3 a nd starts drivi ng the da ta bus, MDATA[7:0]. CPU be gins executing by takin g a MIPS soft re set exception. The assertion of CSN[0] wi ll occur no so oner tha n 1 6 clo ck cycles a fter the RC3243 4 s ampl es RSTN n egated (i.e., step 5).
Figure 5 Externally Initiated Warm Reset AC Timing Waveform
Signal
Symbol
Reference Edge
266MHz Min Max
300MHz Min Max
350MHz Min Max
400MHz Min Max
Unit
Timing Diagram Reference
Memory Bus - DDR Access DDRDATA[15:0] Tskew_7g Tdo_7k2 DDRDM[1:0] DDRDQS[1: 0] Tdo_7l Tdo_7i DDRDQSx DDRCKP DDRCKP DDRDQSx 0 1. 2 1. 2 -0.75 1. 0 0. 9 1.9 1.9 0.75 4. 0 0 1.0 1.0 -0.75 1. 0 0.81 1.7 1.7 0.75 4. 3 0 0. 7 0. 7 -0. 7 1. 0 0.7 1.5 1.5 0.7 4. 0 0.0 0.5 0.5 -0. 7 1. 0 0.6 1.4 1.4 0.7 4. 0 ns ns ns ns ns See Figures 6 and 7.
DDRADDR[13:0] , Tdo_7m DDRBA[1:0], DDRCASN, DDRCKE, DDRCSN, DDRRASN, DDRWEN
1. Meets DDR timing 2. Setup times
Table 7 DDR SDRAM Ti ming Characteristics
requir ements for 150MHz clock rate DDR SDRAMs with 300 ps remaining mar gin to compensate for PCB propagation mismatches, which is adequate to guarantee functional timing, provided the RC32434 DDR layout guidelines ar e adhered to. are calculated as applicable clock period - T do max. F or example, if the DDR is running at 266MHz, it uses a 133MHz input clock. The per iod for a 133MHz clock is 7.5ns. If the Tdo max value is 4.6n the TI S parameter is 7.5ns minus 4.6ns = 2.9ns. The DDR spec for this parameter is 1ns, so ther e is 1.9ns of slack left over for board s, propagation. Calculations for TDS are similar, but since this parameter is taken relative to the DDRDQS signals, which are r eferenced on both edges, the effective period with a 133MHz input clock is only 3.75ns. So, if the max Tdo is 1.9ns, we have 3.75ns minus 1.9ns = 1.85ns for TDS . The DDR data sheet specs a value of 0.5ns for 266MHz, so this leaves 1.35ns slack for board propagation delays.
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IDT RC32434
D DRCK P DDR CKN Td o_ 7m DDR CSN Tdo 7m _ DDRA DDR 3 ] [1 :0 Ro wA Td o_ 7m
1 DDRC MD
CA ol 0
Co A l2
R ow B
NO P
A CTV
NO P
RD
RD
N OP
NO P
P REC HG NO P
A CT V
NO P
D DRCK E Tdo 7m _ DD RB A[1 ] :0 DDR DM[1 ] :0 B NK x B NK x B NK x B NKx B NK x
DDRD QS (id al) x e DD RDA TA 5 ] 2 (id al) [1 :0 e Tac (m ) in DDRD QS (m x in) Tskew g _7 D 0 D1 D 2 Tac (m ax) D3 D0 D1 D2 D3
2 DDR DAT A[1 5:0]
DDR DQ Sx (m ax) Tske w_ 7g D 0 D1 D2
2 DDR DAT A[1 5:0]
D3
1 2
DDRCM con ns DDR D tai RA SN, DDR CA SN a nd DDRW N. E DD RDA TA i e s ithe 3 bits o 16 its w e de en r 2r -b id p din o th DB gn e W co ntro bi i DDR Reg l tn C iste r
( see Ch ap r 7 DD Co te , R ntro r, in th RC3 43 U r Re re ce Ma lle e 2 4 se fe n nu ). al
Figure 6 DDR SDRAM AC Timing Waveform - SDRAM Read Access
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IDT RC32434
DD RC KP D DR CKN Tdo_7m D DR CSN Tdo_7m D DR AD DR [13:0]
1 D DRC MD
R owA Tdo_7m N OP AC TV N OP
C A0 ol W R
C A2 ol W R N OP N OP NOP NOP NOP
DD RC KE Tdo_7m D DR BA[1:0] BN Kx BNKx
DD RDQSx Tdo_7l Tdo_7l D DRD M[1:0] F F DM DM 0 1 D M3 DM 2 FF
D DR DQSx
T do_7k D DR DATA[15:0]2
1 2
Tdo_7k D1 D2 D3
D0
DD RC MD contains DD RR ASN, DD RC ASN and D DR EN W .
DD RD ATA is either 32-bits or 16-bits wide depending on the D BW control bit in DD RC Register (see Chapter 7, D DR Controller, in the RC32434 User Reference Manual).
Figure 7 DDR SDRAM Timing Waveform -- Write Access
Signal
Symbol
Reference Edge
266MHz Min Max
300MHz Min Max
350MHz Min Max
400MHz Min Max
Unit
Conditions
Timing Diagram Reference See Figures 8 and 9.
Memory and Peripheral Bus1 MADDR[21:0] Tdo_8a Tdz_8a2 Tzd_8a MADDR[25:22]
2
EXTCLK rising
0.4 -- --
4.5 -- -- 4.5 -- --
0.4 -- -- 0.4 -- --
4.5 -- -- 4.5 -- --
0.4 -- -- 0.4 -- --
4.5 -- -- 4.5 -- --
0.4 -- -- 0.4 -- --
4.5 -- -- 4.5 -- --
ns ns ns ns ns ns
Tdo_8b Tdz_8b
2
EXTCLK rising
0.4 -- --
Tzd_8b2
Table 8 Memory and Peri pheral Bus AC Timing Characteristics (Part 1 of 2)
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IDT RC32434
Reference Edge
Signal MDATA[7:0]
Symbol Tsu_8c Thld_8c Tdo_8c Tdz_8c
2
266MHz Min 6. 0 0 0.4 0 0.4 Max -- -- 4.5 0.5 3.3 -- 3.8 -- -- 3.8 -- -- -- -- -- 4.0 -- -- 3.8 -- -- 4.0 -- -- 3.7 -- --
300MHz Min 6. 0 0 0.4 0 0.4 6.66 0.4 -- -- 0.4 -- -- 6.5 0
2(EXTCLK)
350MHz Min 6. 0 0 0.4 0 0.4 6.66 0.4 -- -- 0.4 -- -- 6.5 0
2(EXTCLK)
400MHz Min 6. 0 0 0.4 0 0.4 6.66 0.4 -- -- 0.4 -- -- 6.5 0
2(EXTCLK)
Max -- -- 4.5 0.5 3.3 -- 3.8 -- -- 3.8 -- -- -- -- -- 4.0 -- -- 3.8 -- -- 4.0 -- -- 3.7 -- --
Max -- -- 4.5 0.5 3.3 -- 3.8 -- -- 3.8 -- -- -- -- -- 4.0 -- -- 3.8 -- -- 4.0 -- -- 3.7 -- --
Max -- -- 4.5 0.5 3.3 -- 3.8 -- -- 3.8 -- -- -- -- -- 4.0 -- -- 3.8 -- -- 4.0 -- -- 3.7 -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Conditions
Timing Diagram Reference See Figures 8 and 9 (cont.).
EXTCLK rising
Tzd_8c 2 EXTCLK BDI RN
3
Tper_8d Tdo_8e Tdz_8e
2
none EXTCLK rising
7.5 0.4 -- --
Tzd_8e2 BOEN Tdo_8f Tdz_8f WAITACKN4
2 2
EXTCLK rising
0.4 -- --
Tzd_8f
Tsu_8h Thld_8h Tpw_8h
2
EXTCLK rising
6.5 0
none EXTCLK rising
2(EXTCLK)
CSN[3:0]
Tdo_8i Tdz_8i 2 Tzd_8i
2
0.4 -- --
0.4 -- -- 0.4 -- -- 0.4 -- -- 0.4 -- --
0.4 -- -- 0.4 -- -- 0.4 -- -- 0.4 -- --
0.4 -- -- 0.4 -- -- 0.4 -- -- 0.4 -- --
RWN
Tdo_8j Tdz_8j
2
EXTCLK rising
0.4 -- --
Tzd_8j 2 OEN Tdo_8k Tdz_8k Tzd_8k WEN
2 2
EXTCLK rising
0.4 -- --
Tdo_8l Tdz_8l Tzd_8l
2 2
EXTCLK rising
0.4 -- --
Table 8 Memory and Peri pheral Bus AC Timing Characteristics (Part 2 of 2)
1. The RC32434
pr ovides bus turnaround cycles to prevent bus contention when going from read to write, write to read, and during external bus ownership. For example, there are no cycles where an exter nal device and the RC32434 are both driving. See Chapter 6, Device Controller, in the RC32434 User Reference Manual. this symbol were determined by calculation, not by testing. is programmable. See the External Clock Divider (MDATA[5:4]) description in Table 3 of this data sheet.
2. The values for
3. The frequency of EXTCLK 4. WAITACKN
must meet the setup and hold times if it is synchronous or the minimum pulse width if it is asynchronous.
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Tper_8d EXT CLK Tdo_8a M ADD R[21:0] T do_8b MADDR [25:22] RW N Tdo_8i C SN [3:0] T do_8i Addr[25:22] Addr[21:0]
Thigh_8d
Tlow_8d
W EN Tdo_8k OEN
1111 Tdo_8k
Thld_8c Tdz_8c M DAT A[7:0] Tdo_8e BDIRN Tdo_8f BOEN W AITACKN
R C32 34 4 sa mp s le r ea d d ata
Tsu_8c D ata
Tzd_8c
Tdo_8e
Tdo_8f
Figure 8 Memory and Peripheral Bus AC Timing Waveform -- Read Access
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IDT RC32434
ETL X CK T o_8 d a M D R :0 A D [21 ] T _8 do b MD R A D [25:2 2] T do_ 8j RN W T _8i do A dr[2 d 5:22 ] A dr[2 d 1:0]
C N3 ] S [ :0 T o_ d 8l WN E ON E T _8 do c M A A :0 D T [7 ] B IR DN T _8 do f 11 11
B te E ab y n les
1 111
D ata
BE ON W IT C N A AK
Figure 9 Memory and Peripheral Bus AC Timing Waveform -- Write Access
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IDT RC32434
Signal Ethernet MIIMDC
Symbol
Reference Edge
266MHz Min Max
300MHz Min Max
350MHz Min Max
400MHz Min Max
Unit
Conditions
Timing Diagram Reference
Tper_9a Thigh_9a, Tlow_9a
None
30.0 12.0
-- -- -- -- 300
30.0 12.0 10.0 0.0 10
-- -- -- -- 300
30.0 12.0 10.0 0.0 10
-- -- -- -- 300
30.0 12.0 10.0 0.0 10
-- -- -- -- 300
ns ns ns ns ns
See Figure 10.
MIIMDIO
Tsu_9b Thld_9b Tdo_9b
1
MIIMDC rising
10.0 0. 0 10
Ethernet -- MII Mode MIIRXCLK, MIITXCLK2 Tper_9c Thigh_9c, Tlow_9c Trise_9c, Tfall_9c MIIRXCLK, MIITXCLK2 Tper_9d Thigh_9d, Tlow_9d Trise_9d, Tfall_9d MIIRXD[3:0], MIIRXDV, MIIRXER MIITXD[3:0], MIITXENP, MIITXER Tsu_9e Thld_9e Tdo_9f MIIxRXCLK rising MIIxTXCLK rising None None 399.96 180 -- 39.9 18.0 -- 10.0 10.0 0. 0 400.4 220 3.0 40.0 22.0 2.0 -- -- 25. 0 399.96 180 -- 39.9 18.0 -- 10.0 10.0 0.0 400.4 220 3.0 40.0 22.0 2.0 -- -- 25.0 399.96 180 -- 39.9 18.0 -- 10.0 10.0 0.0 400.4 220 3.0 40.0 22.0 2.0 -- -- 25.0 399.96 180 -- 39.9 18.0 -- 10.0 10.0 0.0 400.4 220 3.0 40.0 22.0 2.0 -- -- 25.0 ns ns ns ns ns ns ns ns ns 100 Mbps 10 Mbps See Figure 10.
Ethernet -- RMII Mode RMIIREFCLK Tper_9i Thigh_9i, Tlow_9i RMIITXEN, RMIITXD[1:0] RMIICRSDV, RMIIRXER, RMIIRXD[1:0]
1. The values for
None
19.9 7.0
20.1 13.0 -- 14.5
19.9 7.0 2.0 5.5
20.1 13.0 -- 14.5
19.9 7.0 2.0 5.5
20.1 13.0 -- 14.5
19.9 7.0 2.0 5.5
20.1 13.0 -- 14.5
ns ns ns ns
See Figure 10.
Tdo_9j Tsu_9k
MIIRXCLK rising
2.0 5.5
Table 9 Ethernet AC Timing Characteristics
this symbol were determined by calculation, not by testing. MIITXCLK) frequency must be equal to or less than 1/2 ICLK (MII RXCLK and MIITXCLK <= 1/2( ICLK)) .
2. The ethernet clock (MIIRXCLK and
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IDT RC32434
Thigh_9a Tper_9a MII MDC Tdo_9b MI IMDIO (output)
Tlow_9a
Tdo_9b
Thld_9b Tsu_9b MIIMDIO (input)
Thigh_9d Tper_9d MIIRXCLK Thld_9e Tsu_9e MIIRXDV, MIIRXD[3:0], MIIRXER Thigh_9d Tper_9d MIITXCLK Tdo_9f Tdo_9f MIITXEN, MIITXD[3:0], MIITXER Thigh_9i Tper_9i RMII REFCLK RMII TXEN, RMII TXD[1:0]
Tdo_9j Tdo_9j
Tlow Tlow_9d
Tlow Tlow_9d
Tlow_9i
Tper_9i Thigh_9i RMII REFCLK Tsu_9k RMII CRS_DV, RMII RXER RMII RXD[1:0] Figure 10 Ethernet AC Timing Waveform
Tlow_9i
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IDT RC32434 266MHz Min Max 300MHz Min Max 350MHz Min Max 400MHz Min Max Timing Diagram Reference
Signal PCI1 PCICLK 2
Symbol
Reference Edge
Unit
Conditions
Tper_10a Thigh_10a, Tlow_10a Tslew_10a
none
15.0 6.0 1.5
30.0 -- 4.0 -- -- 6.0 14.0 --
15.0 6.0 1.5 3.0 0 2.0 -- 2.0
30.0 -- 4.0 -- -- 6.0 14.0 --
15.0 6.0 1.5 3.0 0 2.0 -- 2.0
30.0 -- 4.0 -- -- 6.0 14.0 --
15.0 6.0 1.5 3.0 0 2.0 -- 2.0
30.0 -- 4.0 -- -- 6.0 14.0 --
ns ns V/ns ns ns ns ns ns
66 MHz PCI
See Figure 11.
PCIAD[31:0], PCIBEN[3:0] , PCIDEVSELN, PCIFRAMEN,PCII RDYN, PCILOCKN, PCIPAR, PCIPERRN, PCISTOPN, PCITRDY PCIGNTN[3:0], PCIREQN[3: 0]
Tsu_10b Thld_10b Tdo_10b Tdz_10b 3 Tzd_10b
3
PCICLK rising
3.0 0 2.0 -- 2.0
Tsu_10c Thld_10c Tdo_10c
3
PCICLK rising
5.0 0 2.0
-- -- 6.0 -- -- -- -- -- 6.0 11.1
5.0 0 2.0 4000 (CLK) 2(CLK) 6(CLK) 3.0 0 2.0 4.7
-- -- 6.0 -- -- -- -- -- 6.0 11.1
5.0 0 2.0 4000 (CLK) 2(CLK) 6(CLK) 3.0 0 2.0 4.7
-- -- 6.0 -- -- -- -- -- 6.0 11.1
5.0 0 2.0 4000 (CLK) 2(CLK) 6(CLK) 3.0 0 2.0 4.7
-- -- 6.0 -- -- -- -- -- 6.0 11.1
ns ns ns ns ns ns ns ns ns ns See Figure 11 See Figures 15 and 16
PCIRSTN (out- Tpw_10d put) 4 PCIRSTN (input) 4,5 PCISERRN6
None None PCIRSTN falling PCICLK rising
4000 (CLK) 2(CLK) 6(CLK) 3.0 0 2.0
Tpw_10e 3 Tdz_10e 3 Tsu_10f Thld_10f Tdo_10f
6
PCIMUI NTN
1. This PCI
Tdo_10g
PCICLK rising
4.7
Table 10 PCI AC Timing Characteristics
interface conforms to the PCI Local Bus Specification, Rev 2.2. or less than two times ICLK (PCICLK <= 2(ICLK)) with a maximum PCICLK of 66 MHz.
2. PCICLK must be equal to 3. The
values for this symbol were determined by calculation, not by testing. in host mode and an input in satellite mode. open collector I/O types. the PCI delay specification from reset asserted to outputs floating, the PCI reset should be logically combined with the COLDRSTN input, instead of input on PCIRSTN.
4. PCIRSTN is an output 5. To meet
6. PCISERRN and PCIMUINTN use
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Thigh_10a Tper_10a PCICLK Tdo_10b Bussed output Tdo_10c Point to point output Thld_10b Tsu_10b Bussed input Tsu_10c Point to point input
valid valid
Tlow_10a
Tdz_10b
Tzd_10b
Thld_10c
Figure 11 PCI AC Timing Waveform
COLDRSTN
cold reset
(tri -state)
Tpw_10d
PCI interface enabled
PCIRSTN (out put) RSTN
warm r eset
Note: During and after cold reset, PCIRSTN is tri-stated and requires a pull-down to reach a low state. After the PCI interface is enabled in host mode, PCIRSTN will be dr iven either high or low depending on the reset state of the RC32434.
Fi gure 12 PCI AC Timing Waveform -- PCI Reset in Host Mode
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CLKP Tpw_10e PCIRSTN (input) RSTN Tdz_10e MDATA[15:0] PCI bus signals Figure 13 PCI AC Timing Waveform -- PCI Reset in Satel lite Mode
warm reset
Signal GPIO GPIO[13:0]
1. The values for
Symbol
Reference Edge
266MHz Min Max
300MHz Min Max
350MHz Min Max
400MHz Min Max
Unit
Conditions
Timing Diagram Reference
Tpw_13b1
None
2(ICLK)
--
2(ICLK)
--
2(ICLK)
--
2(ICLK)
--
ns
See Figure 14.
Table 11 GPI O AC Timing Characteri stics
this symbol were determined by calculation, not by testing.
GPIO (asynchronous input) Tpw_13b Figure 14 GPIO AC Timing Waveform
Signal SPI1 SCK
Symbol
Reference Edge
266MHz Min Max
300MHz Min Max
350MHz Min Max
400MHz Min Max
Unit
Conditions
Timing Diagram Reference
Tper_15a Thigh_15a, Tlow_15a
None
100 40
166667 83353
100 40
166667 83353
100 40
166667 83353
100 40
166667 83353
ns ns
SPI SPI
See Figures 15, 16, and 17.
Tabl e 12 SPI AC Timing Characteristics (Part 1 of 2)
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Reference Edge
Signal SDI
Symbol Tsu_15b Thld_15b
266MHz Min 60 60 0
2(ICLK)
300MHz Min 60 60 0
2(ICLK)
350MHz Min 60 60 0
2(ICLK)
400MHz Min 60 60 0
2(ICLK)
Max -- -- 60 --
Max -- -- 60 --
Max -- -- 60 --
Max -- -- 60 --
Unit ns ns ns ns
Conditions SPI SPI SPI Bit I/O
Timing Diagram Reference See Figures 15, 16, and 17.
SCK rising or falling SCK rising or falling None
SDO SCK, SDI, SDO
1. In
Tdo_15c Tpw_15e
Tabl e 12 SPI AC Timing Characteristics (Part 2 of 2)
SPI mode, the SCK period and sampling edge are pr ogrammable. In PCI mode, the SCK per iod is fixed and the sampling edge is rising.
Thigh_15a Tper_15a SCK
Tlow_15a
Thld_15b Tsu_15b SDI
MSB bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 LSB
Tdo_15c SDO
MSB bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 LSB
Contr ol bits CPOL = 0, CPHA = 0 in the SPI Contr ol Register, SPC.
Figure 15 SPI AC Timing Waveform -- Clock Polarity 0, Clock Phase 0
Thigh_15a
Tper_15a SCK Tsu_15b SDI
MSB bit 6 bit 5 bit 4
Tlow_15a
Thld_15b
bit 3 bit 2 bit 1 LSB
Tdo_15c SDO
MSB bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 LSB
Control bits CPOL = 0, CPHA = 1 in the SPI Control Register, SPC.
Figure 16 SPI AC Timing Waveform -- Clock Polarity 0, Clock Phase 1
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SCK, SDI, SDO (input) Tpw_15e Figure 17 SPI AC Timing Waveform -- Bit I/O Mode
Signal
Symbol
Reference Edge
266MHz Min Max
300MHz Min Max
350MHz Min Max
400MHz Min Max
Unit
Conditions
Timing Diagram Reference
EJTAG and JTAG JTAG_TCK Tper_16a Thigh_16a, Tlow_16a JTAG_TMS1, Tsu_16b JTAG_TDI Thld_16b JTAG_TDO Tdo_16c Tdz_16c
2
none
25.0 10.0
50.0 25.0 -- -- 11.3 11.3 -- -- --
25.0 10.0 2.4 1.0 -- -- 25.0 2.0 1.0
50.0 25.0 -- -- 11.3 11.3 -- -- --
25.0 10.0 2.4 1.0 -- -- 25.0 2.0 1.0
50.0 25.0 -- -- 11.3 11.3 -- -- --
25.0 10.0 2.4 1.0 -- -- 25.0 2.0 1.0
50.0 25.0 -- -- 11.3 11.3 -- -- --
ns ns ns ns ns ns ns ns ns
See Figure 18.
JTAG_TCK rising JTAG_TCK falling none JTAG_TCK rising
2.4 1.0 -- -- 25.0 2.0 1.0
JTAG_TRST_ Tpw_16d2 N EJTAG_TMS1 Tsu_16e Thld_6e
1. The
Table 13 JTAG AC Timing Characteristics
JTAG specification, IEEE 1149.1, recommends that both JTAG_TMS and EJT AG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Other wise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a r ising edge of JTAG_TCK when either JTAG_TMS or EJTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test- Logic-Reset state. this symbol were determined by calculation, not by testing.
2. The values for
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Tlow_16a Thigh_16a JTAG_TCK Thld_16b Tsu_16b JTAG_TDI Thld_16b Tsu_16b JTAG_TMS Thld_16e Tsu_16e EJTAG_TMS Tdo_16c JTAG_TDO Tpw_16d JTAG_TRST_N Figure 18 JTAG AC Timing Wavefor m Tdz_16c Tper_16a
The IEEE 1149.1 specif ication requires that the JTAG and EJTAG TAP controllers be reset at power-up whether or not the interfaces are used for a boundary scan or a probe. Reset can occur through a pull-down resistor on JTAG_TRST_N if the probe is not connected. However, on-chip pull-up resistors are implemented on the RC32434 due to an IEEE 1149.1 requirement. Having on-chip pull-up and external pull-down resistors for the JTAG_TRST_N sig nal requires special care in the design to ensure that a valid logical level is provided to JTAG_TRST_N, such as using a small external pull-down resistor to ensure this level overrid es the on-chip pull-up. An alternative is to use an active power-up reset circuit for JTAG_TRST_N, which driv es JTAG_TRST_N lo w only at power-up and then holds JTAG_TRST_N hig h afterwards with a pull-up resistor. Figure 19 shows the electrical connection of the EJTAG probe target system connector.
VD D
P l-up ul
R 32 C 434 J A _T S _ T G RTN JA _ D T GT I JA _ D T GT O ET GT S JA _ M J A _T K TG C
P l-up ul
T S* RT TI D
S s-res. erie
1
GD N GD N GD N GD N GD N Vc c IO GD N
TO D TS M TK C RT S* DT I N no conn ect
P u l - d o wn l
R et (s ft ard es o /h )
Ohe res t tr e s rc s ou e
Vc v ag c IO olt e r ere c ef n e GD N
T rg S st a et y em R et C uit es irc
Figure 19 Target System Electrical EJTAG Connection
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Using the EJTAG Probe In Figure 19, the pull-up resistors for JTAG_TDO and RST*, the pull-down resistor for JTAG_TRST_N, and the series resistor for JTAG_TDO must be adjusted to the specific design. However, the recommended pull-up/down resistor is 1.0 k because a low value reduces crosstalk on the cable to the connector, allowing higher JTAG_TCK frequencies. A typic al value for the series resistor is 33 . Recommended resistor values have 5% tolerance. If a probe is used, the pull-up resistor on JTAG_TDO must ensure that the JTAG_TDO level is high when no probe is connected and the JTAG_TDO output is tri-stated. This requirement allows reliable connection of the probe if it is hooked-up when the power is already on (hot plu g). The pull-up resistor value of around 47 k should be sufficient. Optional diodes to protect against overshoot and undershoot voltage can be added on the signals of the chip wit h EJTAG. If a probe is used, the RST* signal must have a pull-up resistor because it is controlle d by an open-collector (OC) driver in the probe, and thus is actively pulled low only. The pull-up resis tor is responsible for the high valu e when not driven by the probe of 25pF. The in put on the target system reset circuit must be able to accept the rise time when the pull-up resistor charges the capacitance to a high logical level. Vcc I/O must connect to a voltage reference that drops rapidly to belo w 0.5V when the target system loses power, even wit h a capacitive lo ad of 25pF. The probe can thus detect the lost power condition. For additional information on EJTAG, refer to Chapter 17 of the RC32434 User Reference Manual.
Phase-Locked Loop (PLL)
The phase-locked loop (PLL) multip lies the external oscillator input (pin CLK) according to the parameter provided by the boot configuration vector to create the processor clock (PCLK). Inherently, PLL circuits are only capable of generating clock frequencies within a limited range. PLL Filters It is recommended that the system designer provide a filt er network of passive components for the PLL analog and digital power supplie s. The PLL circuit power and PLL circuit ground should be isolated from power and ground with a filter circuit such as the one shown in Figure 20. Because the optimum values for the filter components depend upon the application and the system noise environment, these values should be considered as starting points for further experimentation within your specific application.
10 ohm 1 Vcc 10 F Vss 0.1 F 100 pF RC32434 VccPLL VccPLL VssPLL VssPLL Figure 20 PLL Filter Circuit for Noisy Environments
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Recommended Operating Supply Voltages
Symbol Vss VssPLL VccI/O VccSI/O (DDR) VccPLL VccAPLL VccCore DDRVREF VTT 3
1. SSTL_2
Parameter Common ground PLL ground I/O supply except for SSTL_21 I/O supply f or SSTL_2 PLL supply (digital) PLL supply (analog) Internal logic supply
1
Minimum 0
Typical 0
Maximum 0
Unit V
3.135 2.375 1.1 3.135 1.1 0.5(VccSI/O) DDRVREF - 0.04
3.3 2.5 1. 2 3.3 1. 2 0.5(VccSI/O) DDRVREF
3.465 2.625 1.3 3.465 1.3 0.5(VccSI/O) DDRVREF + 0.04
V V V V V V V
2
SSTL_2 input reference voltage SSTL_2 termination voltage
Table 14 RC32434 Operating Voltages
I/O s are used to connect to DDR SDRAM. noise on DDRVREF may not exceed 2% DDRVREF (DC).
2. Peak-to-peak AC 3. V TT
of the SSTL_2 tr ansmitting device must track DDRVREF of the receiving device.
Recommended Operating Temperatures
Grade Commercial Industrial Temperature 0C to +70C Ambient -40C to +85C Ambient Table 15 RC32434 Operating Temperatures
Capacitive Load Deration
Refer to the 79RC32434 IBIS Model on the IDT web site (www.idt.com).
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Power-on Sequence
Three power-on sequences are given below. Sequence #1 is recommended because it will prevent I/O conflicts and will also allo w the input signals to propagate when the I/O powers are brought up. Note: The ESD diodes may be damaged if one of the voltages is applied and one of the other volt ages is at a ground level. A. Recommended Sequence t2 > 0 whenever possible (V c cCore) t1 - t2 can be 0 (Vcc SI/O followed by Vcc I/O)
V c cI/O 3.3V Vcc SI/O 2.5V V c cCore 1.2V
VccI/O -- 3.3V VccSI/O -- 2.5V VccCore - - 1.2V
t2 t1
Time
B. Reverse Volt age Sequence If sequence A is not feasib le, then Sequence B can be used: t1 <50ms and t2 <50ms to prevent damage.
Vcc3.3 VccI/O Vcc2.5 VccSI/O
VccCore Vcc1.2
VccI/O -- 3.3V VccSI/O -- 2.5V VccCore -- 1.2V
t1
Time t2
C. Simultaneous Power-up VccI/O, VccSI/O, and VccCore can be powered up simultaneously.
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Consumption Power Consumption
Parameter 266MHz Typ. Icc I/O Icc SI/O (DDR) Icc Core, Icc PLL Normal mode Standby mode 1 Power Normal Dissipation mode Standby mode 1
1. The RC32434 enter
300MHz Typ. 220 75 350 240 1.36 0.78 Max. 275 90 550 -- 1.90 --
350MHz Typ. 225 85 400 260 1.45 0.84 Max. 280 100 610 -- 2.02 --
400MHz Typ. 230 95 450 280 1.54 0.90 Max. 285 110 670 -- 2.15 --
Unit
Max. 270 85 510 -- 1.82 --
Conditions CL = 35 pF Tambi ent = 25 oC Max. values use the maximum voltages listed in Table 14. Typical values use the typical voltages listed in that table. Note: For additional information, see Power Considerations for IDT Processors on the IDT web site www.idt.com.
215 70 325 220 1.27 0.73
mA mA mA mA W W
Table 16 RC32434 Power Consumption
Standby mode by executing WAIT instructions. Minimal I/O switching is assumed. On-chip logic outside the CPU core continues to function.
Power Curve
The following graph contain s a power curve that shows power consumption at various core frequencies.
Typical Power Curve
1.60 1.55 1.50 Power (W) 1.45 1.40 1.35 1.30 1.25 266 300 350 400
Core Frequenc y (MHz)
Figure 21 RC32434 Typical Power Usage
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DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 14. Note: See Table 2, Pin Characteristics, for a complete I/O listing.
I/O Type LOW Drive Output HIGH Drive Output Schmitt Trigger Input (STI) SSTL_2 (f or DDR SDRAM) Parameter IOL IO H IOL IO H VI L VIH IOL I OH VIL VIH PCI IOH (AC) Switching Min. -- -- -- -- -0.3 2.0 7.6 -7.6 -0.3 0.5(VccSI/O) + 0.18 -12(VccI/O) -17.1(VccI/O - VOUT ) Typical 14.0 -12.0 41.0 -42.0 -- -- Max. -- -- -- -- 0.8 Vcc I/O + 0.5 Unit mA mA mA mA V V mA mA V V mA mA -- mA mA mA mA mA V V pF -- Vcc (max) Vcc (max) 0 < V OUT < 0.3(VccI/O) 0.3(Vcc I/O) < VOUT < 0.9(VccI/O) 0.7(VccI/O) 0.7(V ccI/O) < VOU T < VccI/O VccI/O > VOUT > 0.6(VccI/O) 0.6(Vcc I/ O) > VOUT > 0.1(VccI/O) VOU T = 0.18(VccI/O) 0.18(VccI/O) > VOUT > 0 Conditions VOL = 0.4V VO H = 1.5V VOL = 0.4V VO H = 1.5V -- -- VOL = 0.5V VOH = 1.76V
-- -- -- -- -- -- -- -- -- -- --
--
-- --
0.5(VccSI /O) - 0.18 VccSI /O + 0.3 -- -- -32(VccI/O) See Note 1 -- -- +38(VccI/O) See Note 2 0.3(VccI /O) 5.5 8.0 + 10 + 10
--
16(Vcc I/ O) IOL(AC) Switching +16(VccI/O) +26.7(VOUT) -- -- VIL VIH Capacitance Leakage C IN -0.3 0.5(VccI /O) -- -- --
-- -- --
-- --
Inputs
I/OLEA K W/O Pull-ups/ downs I/ OLE AK WITH Pull-ups/ downs
A A
--
--
+ 80
A
Vcc (max)
Table 17 DC Electrical Characteristics
Note 1: I OH (AC) max = (98/VC C I/O) * (VOU T - V C C I/O) * (VOU T + 0.4V C CI/O) Note 2: I OL (AC) max = (256/V CC I/O) * V OU T * (V CC I/O - V OU T )
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AC Test Conditions
Input Reference V oltage
50 RC32434 Output
.
50
Test Point Value
Parameter Input pulse levels Input rise/fall Input reference level Output reference levels AC test load
SSTL I/O 0 to 2.5 0.8 0.5(VccSI/O) 1.25 35
Other I/O 0 to 3.3 1.0 0.5(VccI/O) 1.5 35
Units V ns V V pF
Figure 22 AC Test Conditions
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Absolute Maximum Ratings
Symbol VC CI/O VC CSI/O (DDR) VC CCore VC CPLL VC CAPLL VinI/O VinSI/O Ta I ndustrial Ta Commercial Ts Parameter I /O supply except f or SSTL_22 I /O supply for SSTL_2 Core Supply Voltage PLL supply (digital) PLL supply (analog) I /O Input Volt age except for SSTL_2 I /O Input Volt age for SSTL_2 Ambient Operating Temperat ure Ambient Operating Temperat ure Storage Temperature
2
Min 1 -0. 6 -0. 6 -0. 6 -0. 6 -0. 6 -0.6 -0.6 -40 0 -40
Max1 4.0 4.0 2.0 2.0 4.0 VccI/O+ 0.5 VccSI/O+ 0.5 +85 +70 +125
Unit V V V V V V V
C C C
Table 18 Absolute Maximum Rati ngs
1. Functional and tested
operating conditions are given in Table 14. Absolute maximum ratings ar e stress r atings only, and functional oper ation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. I/O s are used to connect to DDR SDRAM.
2. SSTL_2
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Signal Package Pin-out -- 256-BGA Signal Pinout for the RC32434
The following table lists the pin numbers, signal names, and number of alternate functions for the RC32434 device. Sig nal names ending with an "_n" or "n" are active when low.
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 Function RWN OEN CSN[ 2] CSN[ 0] MADDR[10] MDATA[6] GPIO[7] GPIO[4] MADDR[16] MADDR[13] Vss PLL JTAG_TDI MADDR[9] MADDR[7] MADDR[5] MADDR[2] BOEN RSTN CSN[ 3] CSN[ 1] MADDR[11] MDATA[1] MDATA[4] GPIO[5] MADDR[17] MADDR[12] Vcc PLL Vss APLL MADDR[8] MADDR[6] MADDR[3] MADDR[1] EXTCLK 1 1 1 Alt Pin E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 Function MIIRXD[3] MIIRXD[2] MIITXD[ 0] MIITXD[ 1] Vcc I/0 Vcc I/0 Vcc I/0 Vcc CORE Vcc CORE Vcc I/0 Vcc DDR Vcc DDR DDRDATA[6] DDRDATA[5] DDRADDR[13] DDRDATA[4] MIITXD[ 2] MIIRXCLK MIITXD[ 3] MIITXENP Vcc I/0 Vss Vss Vss Vcc CORE Vss Vss Vcc DDR DDRDATA[9] DDRDATA[8] DDRDM[0] DDRDATA[7] MIIRXDV Alt Pin J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 Function GPIO[3] JTAG_TCK GPIO[2] EJTAG_TMS Vcc CORE Vss Vss Vss Vss Vss Vcc CORE Vcc CORE DDRCKN DDRVREF DDRCKP DDRDQS[0] JTG_TDO SCK Reserved SDO Vcc I/0 Vcc I/0 Vss Vss Vss Vss Vss Vcc DDR DDRCKE DDRADDR[11] DDRADDR[10] DDRADDR[12] Reserved 1 Alt 1 Pin N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 Function PCIAD[29] PCIAD[28] PCIAD[30] PCIAD[18] PCIREQN[1] PCIREQN[2] PCIIRDYN PCILOCKN PCIPERRN PCIAD[15] PCIAD[11] PCICBEN[0] DDRADDR[5] DDRADDR[4] DDRADDR[3] DDRBA[0] PCIAD[27] PCIAD[26] GPIO[10] PCIAD[20] PCIREQN[3] PCIREQN[0] PCIFRAMEN PCISTOPN PCISERRN PCIAD[14] PCIAD[10] PCIAD[7] PCIAD[4] DDRADDR[0] DDRADDR[2] DDRCSN PCIAD[25] 1 Alt
Table 19 RC32434 Pinout (Part 1 of 2)
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Pin C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 Function BDIRN COLDRSTN WEN MDATA[3] MDATA[5] GPIO[6] MADDR[21] MADDR[18] MADDR[14] JTAG_TMS Vcc APLL CLK MADDR[4] MADDR[0] DDRDATA[0] MIIRXD[0] MIICL MIICRS MIIRXD[1] MDATA[7] MDATA[2] MDATA[0] MADDR[20] MADDR[19] MADDR[15] EXTBCV JTAG_TRSTN WAITACKN DDRDATA[2] DDRDATA[3] DDRDATA[1] 1 Alt Pin G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 Function MIITXER MIIRXER MIITXCLK Vcc I/0 Vss Vss Vss Vss Vss Vss Vcc DDR DDRDM[1] DDRDQS[1] DDRDATA[10] DDRDATA[11] MIIMDIO MIIMDC GPIO[0] GPIO[1] Vcc CORE Vcc CORE Vss Vss Vss Vss Vss Vcc CORE DDRDATA[15] DDRDATA[14] DDRDATA[12] DDRDATA[13] 1 1 Alt Pin L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 Function Reserved GPIO[8] SDI Vcc I/0 Vss Vss Vcc CORE Vss Vss Vss Vcc DDR DDRADDR[9] DDRWEN DDRCASN DDRADDR[8] GPIO[12] PCIAD[31] GPIO[11] GPIO[9] Vcc I/0 Vcc I/0 Vcc I/0 Vcc CORE Vcc CORE Vcc I/0 Vcc DDR Vcc DDR DDRRASN DDRBA[1] DDRADDR[6] DDRADDR[7] 1 1 1 1 Alt Pin R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 Function PCICBEN[3] PCIAD[23] PCIAD[21] PCIAD[17] PCIRSTN PCICBEN[2] PCITRDYN PCICBEN[1] PCIAD[12] PCIAD[8] PCIAD[5] PCIAD[3] PCIAD[0] PCIGNTN[ 2] DDRADDR[1] PCIAD[24] GPIO[13] PCIAD[22] PCIAD[19] PCIAD[16] PCICLK PCIGNTN[ 0] PCIDEVSELN PCIPAR PCIAD[13] PCIAD[9] PCIAD[6] PCIAD[2] PCIAD[1] PCIGNTN[ 1] PCIGNTN[ 3] 1 Alt
Table 19 RC32434 Pinout (Part 2 of 2)
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RC32434 Alternate Signal Functions
Pin A7 A8 B8 C7 H3 H4 J1 GPIO GPIO[ 7] GPIO[ 4] GPIO[ 5] GPIO[ 6] GPIO[ 0] GPIO[ 1] GPIO[ 3] Alter nate MADDR[25] MADDR[22] MADDR[23] MADDR[24] U0SOUT U0SINP U0CTSN Pin J3 L3 M1 M3 M4 P3 T2 GPIO GPIO[2] GPIO[8] GPIO[12] GPIO[11] GPIO[9] GPIO[10] GPIO[13] Alternate U0RTSN CPU PCIGNTN[5] PCIREQN[5] PCIREQN[4] PCIGNTN[4] PCIMUINTN
Table 20 RC32434 Alternate Signal Functions
Power Pins RC32434 P ower P ins
Vcc I/O E5 E6 E7 E10 F5 G5 K5 K6 L5 M5 M6 M7 M10 Table 21 RC32434 Power Pins Vcc DDR E11 E12 F12 G12 K12 L12 M11 M12 Vcc Core E8 E9 F9 H5 H6 H12 J5 J11 J12 L8 M8 M9 Vcc PLL B11 Vcc APLL C12
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IDT RC32434
RC32434 G round Pins
Vs s F6 F7 F8 F10 F11 G6 G7 G8 G9 G10 G11 H7 H8 H9 H10 H11 Table 22 RC32434 Ground Pins Vs s J6 J7 J8 J9 J10 K7 K8 K9 K10 K11 L6 L7 L9 L10 L11 Vs s PLL A11, B12
Signals RC32434 S ignals Listed Alphabetically
The following table lists the RC32434 pins in alphabetical order.
Signal Name BDIRN BOEN CLK COLDRSTN CSN[0] CSN[1] CSN[2] CSN[3]
I/O Type O O I I O O O O
Location C2 B1 C13 C3 A4 B4 A3 B3
Signal Cate gory Memory and Peripheral Bus
System
Memory and Peripheral Bus
Table 23 RC32434 Alphabetical Signal List (Part 1 of 7)
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Signal Name DDRADDR[0] DDRADDR[1] DDRADDR[2] DDRADDR[3] DDRADDR[4] DDRADDR[5] DDRADDR[6] DDRADDR[7] DDRADDR[8] DDRADDR[9] DDRADDR[10] DDRADDR[11] DDRADDR[12] DDRADDR[13] DDRBA[0] DDRBA[1] DDRCASN DDRCKE DDRCKN DDRCKP DDRCSN DDRDATA[0] DDRDATA[1] DDRDATA[2] DDRDATA[3] DDRDATA[4] DDRDATA[5] DDRDATA[6] DDRDATA[7] DDRDATA[8] DDRDATA[9] DDRDATA[10] DDRDATA[11] DDRDATA[12] DDRDATA[13] DDRDATA[14] I/O Type O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Location P14 R16 P15 N15 N14 N13 M15 M16 L16 L13 K15 K14 K16 E15 N16 M14 L15 K13 J13 J15 P16 C16 D16 D14 D15 E16 E14 E13 F16 F14 F13 G15 G16 H15 H16 H14 Signal Cate gory DDR Bus
Table 23 RC32434 Alphabetical Signal List (Part 2 of 7)
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Signal Name DDRDATA[15] DDRDM[0] DDRDM[1] DDRDQS[0] DDRDQS[1] DDRRASN DDRVREF DDRWEN EJTAG_TMS EXTBCV EXTCLK GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] GPIO[11] GPIO[12] GPIO[13] JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRSTN I/O Type I/O O O I/O I/O O I O I I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I O I I Location H13 F15 G13 J16 G14 M13 J14 L14 J4 D11 C1 H3 H4 J3 J1 A8 B8 C7 A7 L3 M4 P3 M3 M1 T2 J2 A12 K1 C11 D12 JTAG / EJTAG General Purpose Input/Output JTAG / EJTAG System Signal Cate gory DDR Bus
Table 23 RC32434 Alphabetical Signal List (Part 3 of 7)
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Signal Name MADDR[0] MADDR[1] MADDR[2] MADDR[3] MADDR[4] MADDR[5] MADDR[6] MADDR[7] MADDR[8] MADDR[9] MADDR[10] MADDR[11] MADDR[12] MADDR[13] MADDR[14] MADDR[15] MADDR[16] MADDR[17] MADDR[18] MADDR[19] MADDR[20] MADDR[21] MDATA[0] MDATA[1] MDATA[2] MDATA[3] MDATA[4] MDATA[5] MDATA[6] MDATA[7] I/O Type O O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O Location C15 B16 A16 B15 C14 A15 B14 A14 B13 A13 A5 B5 B10 A10 C10 D10 A9 B9 C9 D9 D8 C8 D7 B6 D6 C5 B7 C6 A6 D5 Signal Cate gory Memory and Peripheral Bus
Table 23 RC32434 Alphabetical Signal List (Part 4 of 7)
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Signal Name MIICL MIICRS MIIMDC MIIMDIO MIIRXCLK MIIRXD[0] MIIRXD[1] MIIRXD[2] MIIRXD[3] MIIRXDV MIIRXER MIITXCLK MIITXD[0] MIITXD[1] MIITXD[2] MIITXD[3] MIITXENP MIITXER OEN PCIAD[0] PCIAD[1] PCIAD[2] PCIAD[3] PCIAD[4] PCIAD[5] PCIAD[6] PCIAD[7] PCIAD[8] PCIAD[9] PCIAD[10] PCIAD[11] PCIAD[12] PCIAD[13] PCIAD[14] PCIAD[15] PCIAD[16] I/O Type I I O I/O I I I I I I I I O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Location D2 D3 H2 H1 F2 D1 D4 E2 E1 G1 G3 G4 E3 E4 F1 F3 F4 G2 A2 R14 T14 T13 R13 P13 R12 T12 P12 R11 T11 P11 N11 R10 T10 P10 N10 T5 Memory and Peripheral Bus PCI Bus Interface Signal Cate gory Ethernet Interface
Table 23 RC32434 Alphabetical Signal List (Part 5 of 7)
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Signal Name PCIAD[17] PCIAD[18] PCIAD[19] PCIAD[20] PCIAD[21] PCIAD[22] PCIAD[23] PCIAD[24] PCIAD[25] PCIAD[26] PCIAD[27] PCIAD[28] PCIAD[29] PCIAD[30] PCIAD[31] PCIBEN[0] PCIBEN[1] PCIBEN[2] PCIBEN[3] PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[0] PCIGNTN[1] PCIGNTN[2] PCIGNTN[3] PCIIRDYN PCILOCKN PCIPAR PCIPERRN PCIREQN[0] PCIREQN[1] PCIREQN[2] PCIREQN[3] PCIRSTN PCISERRN I/O Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Location R5 N4 T4 P4 R4 T3 R3 T1 R1 P2 P1 N2 N1 N3 M2 N12 R9 R7 R2 T6 T8 P7 T7 T15 R15 T16 N7 N8 T9 N9 P6 N5 N6 P5 R6 P9 Signal Cate gory PCI Bus Interface
Table 23 RC32434 Alphabetical Signal List (Part 6 of 7)
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Signal Name PCISTOPN PCITRDYN RSTN RWN SCK SDI SDO Vcc APLL Vcc Core I/O Type I/O I/O I/O O I/O I/O I/O Location P8 R8 B2 A1 K2 L4 K4 C12 E8, E9, F9, H5, H6, H12, J5, J11, J12, L8, M8, M9 E11, E12, F12, G12, K12, L12, M11, M12 E5, E6, E7, E10, F5, G5, K5, K6, L5, M5, M6, M7, M10 B11 F6, F7, F8, F10, F11, G6, G7, G8, G9, G10, G11, H7, H8, H9, H10, H11, J6, J7, J8, J9, J10, K7, K8, K9, K10, K11, L6, L7, L9, L10, L11 B12 A11 I O D13 C4 K3, L1, L2 Table 23 RC32434 Alphabetical Signal List (Part 7 of 7) Memory and Peripheral Bus Ground Power System Memory and Peripheral Bus Serial Peripheral Interface Signal Cate gory PCI Bus Interface
Vcc DDR
Vcc I /O
Vcc PLL Vss
Vss APLL Vss PLL WAITACKN WEN Reserved
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Package CABGA RC32434 P ackage Drawing -- 256-pin CABGA
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Package RC32434 Package Drawing
-- Page Two
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Ordering Information
79RCXX Product Type YY Operating Voltage XXXX Device Type 999 Speed A Package A Temp range/ Process
Blank I
Commercial Temperature (0C to +70C Ambient) Industrial Temperature (-40 C to +85 C Ambie nt) 256-pin CABGA 266 MHz Pipelin e Clk 300 MHz Pipelin e Clk 350 MHz Pip eline Clk 400 MHz Pip eline Clk Integrated Core Processor
BC 266 300 350 400 434
H 79RC32
1.2V +/- 0.1V Core Voltage 32-bit Embedded Microprocessor
Valid Combinations
79RC32H434 - 266BC, 300BC, 350BC, 400BC 79RC32H434 - 266BCI , 300BCI, 350BCI 256-pin CABGA package, Commercial Temperature 256-pin CABGA package, Industrial Temperature
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